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Any signal that is left uninitialised is given the left most value as an initial value. This is why std_logic starts as 'U'.
Similarly for unconstrained integers, if you didnt initialise them to 0 the left most value is -2^31. When constrained, like this:
signal int : integer range -10 to 10;
It would initialise to -10 in VHDL, but when you synthesise it, it will convert it to 5 bits, and then may initialise it to something else.
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The rule definitely doesn't apply to synthesized VHDL. Unless "init don't care" is specified, all VHDL registered signals are initialized to zero. Because integer is represented by unsigned or signed, it will be also initialized to zero by default.
The behaviour is however different in functional simulation, so you would want to use explicite initializers for registered signals, if congruence behaviour of simulation and synthesized code is intended.
P.S.: I have to correct my statement. The rule applies also to synthesized integer in Quartus. Sorry for the confusion.
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