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Altera_Forum
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15 years ago

VHDL integers initialization and FPGAs

I've started coding in VHDL just less than a year ago - unexperienced student warning! My question is about integer initalization. I own an Altera DE1 board and I've also got some experience wi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

have you tried simulating it? are you sure you're not missing the state change conditions somehow and allowing the counter to freewheel?

When these integers get converted for synthesis their range will be greater than you specified to fit the number of bits, and if you overflow it will have to wait longer before hitting the final conditions.

Do you have a testbench for this code?