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Honored Contributor
Honored ContributorVHDL integers initialization and FPGAs
I've started coding in VHDL just less than a year ago - unexperienced student warning! My question is about integer initalization. I own an Altera DE1 board and I've also got some experience wi...
Altera_ForumHonored Contributor
Honored ContributorI see, that the integer signals are also reset asynchronously, after that, their state won't depend on an initializer anyway.
A strange point is defining reversed integer ranges with downto. Apparently, it's not forbidden by the VHDL standard. But I wonder, if it may confuse the compiler. And I don't understand the purpose.
