Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

VHDL integers initialization and FPGAs

I've started coding in VHDL just less than a year ago - unexperienced student warning! My question is about integer initalization. I own an Altera DE1 board and I've also got some experience wi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I see, that the integer signals are also reset asynchronously, after that, their state won't depend on an initializer anyway.

A strange point is defining reversed integer ranges with downto. Apparently, it's not forbidden by the VHDL standard. But I wonder, if it may confuse the compiler. And I don't understand the purpose.