VHDL integers initialization and FPGAs

I dont understand what the problem is? is it your misunderstanding of initialisation in VHDL?

Any signal that is left uninitialised is given the left most value as an initial value. This is why std_logic starts as 'U'.

Similarly for unconstrained integers, if you didnt initialise them to 0 the left most value is -2^31. When constrained, like this:

signal int : integer range -10 to 10;

It would initialise to -10 in VHDL, but when you synthesise it, it will convert it to 5 bits, and then may initialise it to something else.