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Altera_Forum's avatar
Altera_Forum
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16 years ago

vhdl help

Hi,

In vhdl can we make an pin declared as "inout" to act as input or as output depending on certain condition.

entity rout is

port(

a : inout bit;

b : inout bit;

);

end rout;

i want "b" to act as output when a is input, and "a" as output when "b" is input.

I am using altera quartus 2 9.0 and i am getting this warning.

"Warning: The following nodes have both tri-state and non-tri-state drivers

Warning: Inserted always-enabled tri-state buffer between "a" and its non-tri-state driver.

Warning: Inserted always-enabled tri-state buffer between "b" and its non-tri-state driver."

what can i do to overcome this warning.

It may sound silly but i am a beginner and i need some help in this regard.

17 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    You need a control input, try this(you also need std_logic type instead of bit)

    b <= a when ctrl = '0' else ''Z';

    a <= 'Z' when ctrl = '0' else b;
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    can this warning including "both tri-state and non-tri-state drivers" affect anything?

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    It tells you that you have asked for an io tristate but you are not using it.

    So you must either use it or lose it. If you want it but it is not implemented then contention is inevitable...
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Thanks! But i am wondering it will disappear if I use a symbol 'Z' to assign it?

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    By applying 'Z' you are telling the synthesis tool to use the io tristate buffer located just behind the pin for. It means you - the designer - are going to output from fpga(apply your drive) but at times you want the drive to be from outside(input) in which case the tristate will cut-off your internal drive.

    For the above example:

    a is driven from outside(input) then it drives b(output) when ctrl = '0' else

    b is driven from outside(input) then it drives a(output now).

    If the tool doesn't see this two drive case it will permanently enable the tristate buffer(output only) and then inout port is obsolete.

    If you apply 'Z' to internal nodes(as opposed to output pins) then it is interpreted differently(as muxes).

    another point is that you can apply 'Z' i.e. ask for tristate buffer without having inout but just out:

    out1 <= '1' when .... else 'Z';

    meaning you can cutoff drive so that an external pulldown(or pullup) takes over and hence equivalent to:

    out1 <= '1' when .. else '0'; -- for the pulldown case.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    kaz, I have another problem want to share with you,and also with people visiting this website.That is I got a warning when I simulate my project in RTL using modelsim_altera.The warning is " There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)." The wave was 'U',can't see their values.But when I try to simulate in GTL ,the values showed up.How to deal with this?

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Try and initialise the operands at signal declaration. Simulation tools don't assume an initial value unless it is specified.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    Try and initialise the operands at signal declaration. Simulation tools don't assume an initial value unless it is specified.

    --- Quote End ---

    Values left uninitialised always start at the left most value in the declaration.

    So for std_logic they always start at 'U'

    sybtype myint is integer range -15 to 27; would initialise to -15.

    type statemachine is (idle, state1, state2, state3) would start at idle.