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Honored Contributorvhdl help
Hi,
In vhdl can we make an pin declared as "inout" to act as input or as output depending on certain condition. entity rout is port( a : inout bit; b : inout bit; ); end rout; i want "b" to act as output when a is input, and "a" as output when "b" is input. I am using altera quartus 2 9.0 and i am getting this warning. "Warning: The following nodes have both tri-state and non-tri-state drivers Warning: Inserted always-enabled tri-state buffer between "a" and its non-tri-state driver. Warning: Inserted always-enabled tri-state buffer between "b" and its non-tri-state driver." what can i do to overcome this warning. It may sound silly but i am a beginner and i need some help in this regard.17 Replies
Altera_Forumthanks ,i'll try
- Altera_Forum
normally, its a problem with your code rather than anything to do with quartus
- Altera_Forum
So do you know some common methods to solve it,like modify quartus settings ,the procedure or both?
- Altera_Forum
Without seeing your code, I cant tell you what the problem is.
My previous 2 reasons are just the most common causes of the "output not dependent on inputs" problem. - Altera_Forum
Nice reply!Thanks!
Actually ,there are warnings about some output pins are stuck at GND this happened maybe when I didnot give their inial values.You know I can't give each value for each of them.so how to prevent them from being stuck at GND or synthesized away? - Altera_Forum
It probably means that any logic you have got in there has been synthesised away. Often this can come from unconnected clocks or enables stuck at '0'
- Altera_Forum
Here is another confusing warning: Warning (15610): No output dependent on input pin "RXD".I have already used it like this "receiver PORT MAP (RXD,...,...); and "RSR<=RXD & RSR(7 DOWNTO 1)".How does this warning come from?
- Altera_Forum--- Quote Start --- Try and initialise the operands at signal declaration. Simulation tools don't assume an initial value unless it is specified. --- Quote End --- Values left uninitialised always start at the left most value in the declaration. So for std_logic they always start at 'U' sybtype myint is integer range -15 to 27; would initialise to -15. type statemachine is (idle, state1, state2, state3) would start at idle.
- Altera_Forum
thanks a lot
- Altera_Forum
Try and initialise the operands at signal declaration. Simulation tools don't assume an initial value unless it is specified.
