Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorvhdl help
Hi, In vhdl can we make an pin declared as "inout" to act as input or as output depending on certain condition. entity rout is port( a : inout bit; b : inout bit; );...
Altera_ForumHonored Contributor
Honored ContributorIt probably means that any logic you have got in there has been synthesised away. Often this can come from unconnected clocks or enables stuck at '0'
