Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

vhdl help

Hi, In vhdl can we make an pin declared as "inout" to act as input or as output depending on certain condition. entity rout is port( a : inout bit; b : inout bit; );...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Try and initialise the operands at signal declaration. Simulation tools don't assume an initial value unless it is specified.