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Altera_Forum's avatar
Altera_Forum
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16 years ago

vhdl help

Hi, In vhdl can we make an pin declared as "inout" to act as input or as output depending on certain condition. entity rout is port( a : inout bit; b : inout bit; );...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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Try and initialise the operands at signal declaration. Simulation tools don't assume an initial value unless it is specified.

--- Quote End ---

Values left uninitialised always start at the left most value in the declaration.

So for std_logic they always start at 'U'

sybtype myint is integer range -15 to 27; would initialise to -15.

type statemachine is (idle, state1, state2, state3) would start at idle.