VHDL HC237 3-8 Decoder with latches

Question

Hello, I'm trying to write the VHDL code for chip HC237.  I think I have something written that will work for the most part, but my problem is in dealing with pin GL.  Basically what this chip does is outputs all low if G1 is low or G2 is high.  When GL is low everything runs normally, when GL is high the output is dependent upon what the last inputs (A,B, and C) were when GL was low.  If my description doesn't make since you can check the truth table and it should be cleared up.  Well I have something written that should work for every situation except for when GL goes high.  I know in assembly you can make most anything a subroutine and just jump to that subroutine.  Is it possible to do that in VHDL?  Could I have an if statement that says if GL='1' then jump to this subroutine?  I've attached the code I've written so far.

altera_forum · Answer

There is no such thing as a subroutine in VHDL. That is a programming concept. VHDL describes digital logic.  Try drawing your circuit on paper before describing it in VHDL.

altera_forum · Answer

VHDL does describe digital logic, but doesn't it also use programming concepts to describe the behavior of the digital circuit?  For instance, you can use if then statements, cases, while loops and for loops in VHDL and those are all programming concepts.  What exactly do you mean by drawing out my circuit on paper first?  Draw out all the logic gates that form my circuit?  That is listed in the datasheet for the chip, but there are some components that don't seem to be standard logic gates.

altera_forum · Answer

It is true that HDLs are programming languages. The main difference that software mindset need to realise is that all constructs are settled at compile time into a netlist (circuit). The circuit itself will not run loops or ifs etc. as does sequential processor based software.

Moreover, most statements in HDL are concurrent as they are meant for parallel implementation. Only certain bodies (processes) are there to describe to the compiler the sequential behaviour. Processes are themselves concurrent with each other and with other comb. assignments.

for example you can design a counter in HDL from lowest level of flips and logic, in effect easing up on the compiler, or you may design it by describing (telling compiler) in a process what you want and leave the compiler to decide the implementation.

You can use subroutines e.g. functions(procedures), instantiations to tell the compiler what you want be implemented. In short the HDL is sequential to the compiler but is interpreted into a netlist of parallel circuitry.

Some statements are purely messages to the compiler e.g. for loops are just there to shorten the code and are unfolded into multiple statements at compile time.

Your code looks ok to me (but you need to add I to sensitivity list). Regarding GL input when high then you need to save A,B,C on registers then apply logic as your "I" case statement.

To register A,B,C state you need a separate clocked process to save previous values when GL was zero.

e.g.

clocked process...

if GL = '0' then

A_reg <= A;

B_reg <= B;

C_reg <= C;

end if;

then use A_reg... for your decoding logic process.

altera_forum · Answer

Ok, thanks for the advice and info.

altera_forum · Answer

Hm so do I need to restate my case statement for if GL=1 then?  I attached an updated copy of my code.  The concept makes sense to me but I'm not exactly sure if my implementation is correct.  I just started learning VHDL so I'm still trying to get a decent grasp on it.

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VHDL HC237 3-8 Decoder with latches

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