VHDL HC237 3-8 Decoder with latches

It is true that HDLs are programming languages. The main difference that software mindset need to realise is that all constructs are settled at compile time into a netlist (circuit). The circuit itself will not run loops or ifs etc. as does sequential processor based software.

Moreover, most statements in HDL are concurrent as they are meant for parallel implementation. Only certain bodies (processes) are there to describe to the compiler the sequential behaviour. Processes are themselves concurrent with each other and with other comb. assignments.

for example you can design a counter in HDL from lowest level of flips and logic, in effect easing up on the compiler, or you may design it by describing (telling compiler) in a process what you want and leave the compiler to decide the implementation.

You can use subroutines e.g. functions(procedures), instantiations to tell the compiler what you want be implemented. In short the HDL is sequential to the compiler but is interpreted into a netlist of parallel circuitry.

Some statements are purely messages to the compiler e.g. for loops are just there to shorten the code and are unfolded into multiple statements at compile time.

Your code looks ok to me (but you need to add I to sensitivity list). Regarding GL input when high then you need to save A,B,C on registers then apply logic as your "I" case statement.

To register A,B,C state you need a separate clocked process to save previous values when GL was zero.

e.g.

clocked process...

if GL = '0' then

A_reg <= A;

B_reg <= B;

C_reg <= C;

end if;

then use A_reg... for your decoding logic process.