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Altera_Forum
Honored Contributor
14 years agoThere is no such thing as a subroutine in VHDL. That is a programming concept. VHDL describes digital logic.
Try drawing your circuit on paper before describing it in VHDL.There is no such thing as a subroutine in VHDL. That is a programming concept. VHDL describes digital logic.
Try drawing your circuit on paper before describing it in VHDL.