Altera_Forum
Honored Contributor
8 years ago[VHDL] 'else generate' is not supported ...
Hi All,
I'm receiving the following error during my code compilation:(vcom-1440) Language feature ELSE GENERATE STATEMENT is not supported yet From what Quartus version is this feature supported? Here is my code: gen_flr_cnt : if (tbl(i).sbit = flr_cnt or tbl(i).pbit = flr_cnt or tbl(i).ibit = flr_cnt) generate
i_flr_cnt : entity work.flr_cnt
generic map(
TRSH =>FLR_CNT_TRSH
)
port map(
clk => clk,
rstn => rstn,
clr => cnt_clr,
flr_in => bit_vec(i),
flr_out => flr_cnt_res(i)
);
else generate flr_cnt_res(i) <= '0';
end generate gen_flr_cnt; Thank you!