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Altera_Forum's avatar
Altera_Forum
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8 years ago

[VHDL] 'else generate' is not supported ...

Hi All, I'm receiving the following error during my code compilation: (vcom-1440) Language feature ELSE GENERATE STATEMENT is not supported yet From what Quartus version is this f...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

You are ahead of vhdl standards. You can split generate into two sections:

if true generate

...

end generate;

if false generate

...

end generate;