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Honored Contributor[VHDL] 'else generate' is not supported ...
Hi All, I'm receiving the following error during my code compilation: (vcom-1440) Language feature ELSE GENERATE STATEMENT is not supported yet From what Quartus version is this f...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- You are ahead of vhdl standards. You can split generate into two sections: if true generate ... end generate; if false generate ... end generate; --- Quote End --- Vhdl 2008 supports if..else generate and case generate. Quartus has supported it since at least q15 http://quartushelp.altera.com/15.0/mergedprojects/hdl/vhdl/vhdl_list_2008_vhdl_support.htm
