[VHDL] 'else generate' is not supported ...

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You are ahead of vhdl standards. You can split generate into two sections:

if true generate

...

end generate;

if false generate

...

end generate;

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Vhdl 2008 supports if..else generate and case generate. Quartus has supported it since at least q15

http://quartushelp.altera.com/15.0/mergedprojects/hdl/vhdl/vhdl_list_2008_vhdl_support.htm