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Honored ContributorVHDL - CASE related question
Hello,
This is probably a very fundamental question but I'm a little confused as I am new to this. In VHDL (I'm sure it the same for others too), if I have such a PROCESS: PROCESS(clk) if RISING_EDGE(clk) CASE state IS WHEN stateA THEN state <= stateB; a <= x"0111"; ........ WHEN stateB THEN state <= stateC; b <= "0101"; .... .... .... END CASE END IF In this, if the state=stateA when it the CASE statement was started, will the state signal be changed fom stateA->stateB-> and so on in each CASE statement when the execution flow down through the CASE statement?? If so, how many statements will excute during that clock period? Is there a limit? or only ONE statement will be exceuted in the clock period? If only one statement will be excuted, within each statement, how many assignment operators can be performed within that CASE statement?? Is there a limitation? Thank you very much. P.S: If anybody knows a good text for learning this typ of issues please let me know.16 Replies
Altera_Forum--- Quote Start --- Hi, if you are using quartus ii, you will have vhdl templates for fsm (finite state machine). Find them in Quartus menu when editing VHDL file. Remember : VHDL is NOT a programming langage, VHDL is a description langage You don't write VHDL as you write programs. --- Quote End --- Thank you mmTsuchi. I am using Quartus II. Did not know about the templates. Thank you for that. About that VHDL is a not a programming language, I can understand that it is different from C++/Java/etc., in the sense that it is concurrent, synchronous, etc., but is there something important you need to keep in mind when writing VHDL? For someone new to VHDL and coming from a C++/Java background. Thank you.- Altera_Forum
Hi, if you are using quartus ii,
you will have vhdl templates for fsm (finite state machine). Find them in Quartus menu when editing VHDL file. Remember : VHDL is NOT a programming langage, VHDL is a description langage You don't write VHDL as you write programs. - Altera_Forum--- Quote Start --- The important point with case is that only 1 case ever matches because each case has to be mutually exclusive. Whether it's a variable or signal is irrelavent. The important point is that the process is sensitive to clk only, so the whole process (and hence the case statement) is only executed on a rising edge of the clock, never between clock edges, so the case statement is only executed once. The signals are updated when the process ends and the variables are updated immediatly. If on the other hand the process was sensitive to state, you'd get yourself in an infinite loop:
With this process, because the process is triggered every time state changes, you're going to be swapping state once per delta cycle, and a simulator would halt after it hits it's iteration limit. --- Quote End --- That cleared it up Tricky. Thank you very much.process(state) begin case state is when state_a => state <= state_b; when state_b => state <= state_a; end case; end process; - Altera_Forum--- Quote Start --- Thank you very much that very quick reply FvM. So only the first CASE statement that 'matches' will be excuted and the assignenments will happen after the process? Is this only for signals or variables also? What is I compare the state of a variable (is it possible?), instead of a signal.. in that case I think the value will be updates instantly.. so does it mean the CASE statements will be executed one after other in a signal clock? Thank you. --- Quote End --- The important point with case is that only 1 case ever matches because each case has to be mutually exclusive. Whether it's a variable or signal is irrelavent. The important point is that the process is sensitive to clk only, so the whole process (and hence the case statement) is only executed on a rising edge of the clock, never between clock edges, so the case statement is only executed once. The signals are updated when the process ends and the variables are updated immediatly. If on the other hand the process was sensitive to state, you'd get yourself in an infinite loop:
With this process, because the process is triggered every time state changes, you're going to be swapping state once per delta cycle, and a simulator would halt after it hits it's iteration limit.process(state) begin case state is when state_a => state <= state_b; when state_b => state <= state_a; end case; end process; - Altera_Forum--- Quote Start --- No, according to general VHDL rules for sequential processes. All assignments get valid after the process ends. Unlimited. In addition, in process, you can have multiple assignments to a signal. The last wins. --- Quote End --- Thank you very much that very quick reply FvM. So only the first CASE statement that 'matches' will be excuted and the assignenments will happen after the process? Is this only for signals or variables also? What is I compare the state of a variable (is it possible?), instead of a signal.. in that case I think the value will be updates instantly.. so does it mean the CASE statements will be executed one after other in a signal clock? Thank you.
- Altera_Forum--- Quote Start --- will the state signal be changed --- Quote End --- No, according to general VHDL rules for sequential processes. All assignments get valid after the process ends. --- Quote Start --- how many assignment operators can be performed within that CASE statement?? --- Quote End --- Unlimited. In addition, in process, you can have multiple assignments to a signal. The last wins.
