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The important point with case is that only 1 case ever matches because each case has to be mutually exclusive. Whether it's a variable or signal is irrelavent. The important point is that the process is sensitive to clk only, so the whole process (and hence the case statement) is only executed on a rising edge of the clock, never between clock edges, so the case statement is only executed once. The signals are updated when the process ends and the variables are updated immediatly. If on the other hand the process was sensitive to state, you'd get yourself in an infinite loop:
process(state)
begin
case state is
when state_a =>
state <= state_b;
when state_b =>
state <= state_a;
end case;
end process;
With this process, because the process is triggered every time state changes, you're going to be swapping state once per delta cycle, and a simulator would halt after it hits it's iteration limit.
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That cleared it up Tricky.
Thank you very much.
Honored Contributor
