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Altera_Forum
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16 years ago

VHDL - CASE related question

Hello, This is probably a very fundamental question but I'm a little confused as I am new to this. In VHDL (I'm sure it the same for others too), if I have such a PROCESS: PROC...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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will the state signal be changed

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No, according to general VHDL rules for sequential processes. All assignments get valid after the process ends.

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how many assignment operators can be performed within that CASE statement??

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Unlimited.

In addition, in process, you can have multiple assignments to a signal. The last wins.