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Honored ContributorVHDL - CASE related question
Hello, This is probably a very fundamental question but I'm a little confused as I am new to this. In VHDL (I'm sure it the same for others too), if I have such a PROCESS: PROC...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- will the state signal be changed --- Quote End --- No, according to general VHDL rules for sequential processes. All assignments get valid after the process ends. --- Quote Start --- how many assignment operators can be performed within that CASE statement?? --- Quote End --- Unlimited. In addition, in process, you can have multiple assignments to a signal. The last wins.
