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No, according to general VHDL rules for sequential processes. All assignments get valid after the process ends.
Unlimited.
In addition, in process, you can have multiple assignments to a signal. The last wins.
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Thank you very much that very quick reply FvM.
So only the first CASE statement that 'matches' will be excuted and the assignenments will happen after the process? Is this only for signals or variables also? What is I compare the state of a variable (is it possible?), instead of a signal.. in that case I think the value will be updates instantly.. so does it mean the CASE statements will be executed one after other in a signal clock?
Thank you.
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