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Honored ContributorVery simple Verilog code, but not working on DE2
I am running this simple code, pushing KEY[3] works fine (decrement), but when I push KEY[1] the 7-seg changes with both pushing and releasing and display some random number on the 7-seg.
hex_7seg is just a module to display count on the 7-seg. It works fine for other projects. Looks like the problem is with the if statement. Since when I test KEY[3] instead of KEY[1], the problem will be when I push KEY[3] Any help is appreciated module d1_7seg(KEY, HEX0); input [3:0] KEY; output [6:0] HEX0; reg [3:0] count; always @ ( negedge KEY[3] or negedge KEY[1]) begin if(KEY[1] == 0) begin count <= count + 1; end else begin count <= count - 1; end end hex_7seg (count, HEX0); endmodule3 Replies
Altera_ForumThe RST example creates asynchronous logic, as said. You'll never be able to e.g count reset events under the (RST == 0) condition.
- Altera_Forum
First, thanks. You are right. It works now.
However, I thought that always @ (negedge KEY[3] or negedge KEY[1] ) if (KEY[1] == 0) is similar to always @ (posedge clock or negedge RST) if (RST == 0) which works fine I guess I was wrong ... Thanks again --Mokhtar - Altera_Forum
As a simple fact, you can't have two different edge sensitive triggers for a single counter.
The code actually defines an edge sensitive (synchronous) trigger for KEY[3] and an asynchronous trigger for KEY[1], which doesn't work for a counter. The combination of negedge KEY[1] and if (KEY[1] == 0) is a specific Verilog syntax, that's e.g. used for asynchronous resets. You typically should get a serious synthesis warning like "count[x] doesn't hold it's state between clock edges" indicating, that the counter doesn't work. Facing this fact, you obviously need to use a different method to detect keypress events. The common method is synchronous edge detection utilizing a system clock and comparing present and previous state of a signal.
