Very simple Verilog code, but not working on DE2

As a simple fact, you can't have two different edge sensitive triggers for a single counter.

The code actually defines an edge sensitive (synchronous) trigger for KEY[3] and an asynchronous trigger for KEY[1], which doesn't work for a counter. The combination of negedge KEY[1] and if (KEY[1] == 0) is a specific Verilog syntax, that's e.g. used for asynchronous resets. You typically should get a serious synthesis warning like "count[x] doesn't hold it's state between clock edges" indicating, that the counter doesn't work.

Facing this fact, you obviously need to use a different method to detect keypress events. The common method is synchronous edge detection utilizing a system clock and comparing present and previous state of a signal.