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Altera_Forum's avatar
Altera_Forum
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14 years ago

Very simple Verilog code, but not working on DE2

I am running this simple code, pushing KEY[3] works fine (decrement), but when I push KEY[1] the 7-seg changes with both pushing and releasing and display some random number on the 7-seg. hex_7...
Altera_Forum's avatar
Altera_Forum
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14 years ago

The RST example creates asynchronous logic, as said. You'll never be able to e.g count reset events under the (RST == 0) condition.