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Honored Contributor
Honored ContributorVery simple Verilog code, but not working on DE2
I am running this simple code, pushing KEY[3] works fine (decrement), but when I push KEY[1] the 7-seg changes with both pushing and releasing and display some random number on the 7-seg. hex_7...
Altera_ForumHonored Contributor
Honored ContributorFirst, thanks. You are right. It works now.
However, I thought that always @ (negedge KEY[3] or negedge KEY[1] ) if (KEY[1] == 0) is similar to always @ (posedge clock or negedge RST) if (RST == 0) which works fine I guess I was wrong ... Thanks again --Mokhtar
