Verilog

The expression can't result in a valid syntax, I think. The right-hand-side has a variable length, it can't be assigned to a target with (obviously) fixed length. Furthermore variable ranges are not supported. You should think about an iteration, that copies individual bits.

You might get a registered mux out of that. Really though I would re-write that as a mux if that was your intent since someone picking up your source file might struggle to figure out what it's supposed to do.

Fvm,

I didn't understand your intention yet. Do you mean to select a single bit? [count:0] is a range rather than a bit. Please clarify also the type of the other involved signals.

My intention is same as to select range of bits. From your previous post, you suggest me to do iteration to achieve my intention. However, i fail to do it using for loop. That's why asking for some example.

O.K., select a range of bits. But you can't assign a variable length selection range to a fixed length target. So again, what's the type of involved signals and what kind of assignment is intended for it.

the count(reg) is dependent on input while q is output. it is non blocking assignment. Does blocking or non blocking play an important role in it?

Both of it also 32bit.

module test
(
  input   d,
  input   count, 
  output reg  q
);
integer i;
always @(*)
begin
  for (i=0;i<=count;i=i+1)
    q <= d;
end
endmodule