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Altera_Forum's avatar
Altera_Forum
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15 years ago

Verilog

in verilog, how to do like q <= d[count:0]? reg [3:0] count; thanks
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

My intention is same as to select range of bits. From your previous post, you suggest me to do iteration to achieve my intention. However, i fail to do it using for loop. That's why asking for some example.