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Altera_Forum's avatar
Altera_Forum
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15 years ago

Verilog

in verilog, how to do like q <= d[count:0]? reg [3:0] count; thanks
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

the count(reg) is dependent on input while q is output. it is non blocking assignment. Does blocking or non blocking play an important role in it?

thanks