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Altera_Forum's avatar
Altera_Forum
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15 years ago

Verilog

in verilog, how to do like q <= d[count:0]? reg [3:0] count; thanks
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

You might get a registered mux out of that. Really though I would re-write that as a mux if that was your intent since someone picking up your source file might struggle to figure out what it's supposed to do.