Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorVerilog
in verilog, how to do like q <= d[count:0]? reg [3:0] count; thanks
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Does blocking or non blocking play an important role in it? --- Quote End --- Not in this case, I think. What is the bitwidth of d and q?
