Forum Discussion

Honored Contributor

15 years ago

Verilog

in verilog, how to do like q <= d[count:0]? reg [3:0] count; thanks

Honored Contributor

15 years ago

module test
(
  input   d,
  input   count, 
  output reg  q
);
integer i;
always @(*)
begin
  for (i=0;i<=count;i=i+1)
    q <= d;
end
endmodule