Verilog, System Verilog and SystemC

Question

i confused about these languages.

Can somebody clarify on it:

1. For RTL design, Verilog or System Verilog should be used?Most of the article about System Verilog focus on verification. Which language is easier to user and perform well?

2. If the RTL design is written in Verilog, is it possible to use System Verilog to verify it?

3. Is it possible to mix Verilog and System Verilog in one design? e.g the design previously written in verilog, and realise that some new feature in System Verilog can enhance the performance of previous design.

4. Since System C and System Verilog both also system level design, when to use System C and System Verilog?According to my understanding, System C is used in starting of system design in order to predict the performance of software and hardware while System Verilog is used in verification for RTL.

5. How to determine which portion in a system should go to softcore or hardcore?

Thanks and sorry if asking silly question(s)..

altera_forum · Answer

1. It's still really a matter of preference, but if you're starting out then I recommend System Verilog because it introduces some nice features and enhancements to the language. Yes, most System Verilog texts focus on the nice verification features, but as a standalone HDL it works just fine, and it cleans up a few minor inconsistencies that still exist in earlier Verilog versions.

2. Yes. Well, with something that can interpret SystemVerilog verification code well. Quartus is a little behind in this department, but all Verilog interpretors I've seen that support SV treat Verilog and SV the same: as the modules you define. So it is possible to instantiate a module written in Verilog in a SystemVerilog file.

3. Very much so. There are a few reserved keywords introduced in SystemVerilog, such as "class" and "logic", that you should make sure are not used as variable names such that it would be interpreted incorrectly by a SV compiler.

4. SystemC is not a hardware description language. So although it is very useful for very-high-level simulations of hardware-like functions, any hardware design based on its code will be inefficient and bulky. Stick with Verilog for system design.

5. Hardware is for when you are thinking in terms of what needs to happen on a clock-cycle per clock-cycle basis, or with logic, or any combination of the two. Software is for when you are thinking in terms of completing a series of tasks or steps.

You're welcome, I hope this helps.

altera_forum · Answer

It is very informative for me.

Besides, is there anything that verilog can do and system verilog cant? since a lot of hardware design engineer still use verilog for RTL design.

I read a lot of threads that mention to use system verilog instead of system c for system level design. if in the case of SoC, where it involve the software and hardware, is system verilog have this kind of ability to synthesis(not sure the term to use) it?

altera_forum · Answer

verilog is good, ohters is new.

altera_forum · Answer

A bit of clarification.  Quartus II 9.x supports a subset of SV called 2005.  This is the feature set ratified in 2005.  SV is a subset of Verilog.  SV is primarily used for verification because of the it is a full OO language and supports verification scoreboarding along with a lot of other features.  If you use the free OVM library it should compile with Quartus II.  SystemC can be used to describe hardware but the ASIC based synthesis tools on the market still produce inefficient design netlists.  This is changing.  It is unclear if the FPGA synthesis tools are any better.  SVis a very large language.  In fact, it is actually 6 languages:  constraint language, assertion language, scoreboarding language, etc.  Most people will not have the expertise or patience to use all of these features.

altera_forum · Answer

Great question and great responses. I've been learning SV and enjoy it. I'm switching from AHDL and will be moving to ModelSim to do my simulations. I have mainly been using SV for hardware design.

Thanks,

joe

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Verilog, System Verilog and SystemC

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