Verilog, System Verilog and SystemC

It is very informative for me.

Besides, is there anything that verilog can do and system verilog cant? since a lot of hardware design engineer still use verilog for RTL design.

I read a lot of threads that mention to use system verilog instead of system c for system level design. if in the case of SoC, where it involve the software and hardware, is system verilog have this kind of ability to synthesis(not sure the term to use) it?