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Altera_Forum's avatar
Altera_Forum
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16 years ago

Verilog, System Verilog and SystemC

i confused about these languages. Can somebody clarify on it: 1. For RTL design, Verilog or System Verilog should be used?Most of the article about System Verilog focus on verification. Whi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Great question and great responses. I've been learning SV and enjoy it. I'm switching from AHDL and will be moving to ModelSim to do my simulations. I have mainly been using SV for hardware design.

Thanks,

joe