Verilog, System Verilog and SystemC

1. It's still really a matter of preference, but if you're starting out then I recommend System Verilog because it introduces some nice features and enhancements to the language. Yes, most System Verilog texts focus on the nice verification features, but as a standalone HDL it works just fine, and it cleans up a few minor inconsistencies that still exist in earlier Verilog versions.

2. Yes. Well, with something that can interpret SystemVerilog verification code well. Quartus is a little behind in this department, but all Verilog interpretors I've seen that support SV treat Verilog and SV the same: as the modules you define. So it is possible to instantiate a module written in Verilog in a SystemVerilog file.

3. Very much so. There are a few reserved keywords introduced in SystemVerilog, such as "class" and "logic", that you should make sure are not used as variable names such that it would be interpreted incorrectly by a SV compiler.

4. SystemC is not a hardware description language. So although it is very useful for very-high-level simulations of hardware-like functions, any hardware design based on its code will be inefficient and bulky. Stick with Verilog for system design.

5. Hardware is for when you are thinking in terms of what needs to happen on a clock-cycle per clock-cycle basis, or with logic, or any combination of the two. Software is for when you are thinking in terms of completing a series of tasks or steps.

You're welcome, I hope this helps.