Verilog, System Verilog and SystemC

A bit of clarification. Quartus II 9.x supports a subset of SV called 2005. This is the feature set ratified in 2005. SV is a subset of Verilog. SV is primarily used for verification because of the it is a full OO language and supports verification scoreboarding along with a lot of other features. If you use the free OVM library it should compile with Quartus II. SystemC can be used to describe hardware but the ASIC based synthesis tools on the market still produce inefficient design netlists. This is changing. It is unclear if the FPGA synthesis tools are any better. SVis a very large language. In fact, it is actually 6 languages: constraint language, assertion language, scoreboarding language, etc. Most people will not have the expertise or patience to use all of these features.