Using DCFIFO from Quartus IP in Qsys with avalon mm at write side

Question

Hi allHi Iam workign with  Cyclone v FPGA.I am using DCFIFO from Quartus IP mapped to avalon mm interface where write side of FIFO is connected to avalon mm and read side is to the custom IP in QSYS system. I need a condition such that once FIFO is full with continuose writes, the avalon mm should wait until the FIFO is read from custom IP side (ie FIFO wrfull is deasserted )such that data write happens after that. How can I acheive this ? How to manipulate Avalon mm bus writes ?

anandraj_s_intel · Answer

Hi Athira,Yes, you can do that using some logic in your custom component.Interface your DCFIFO and custom IP.Write a logic in custom IP to control DCFIFO read/write.Refer below links design example and DCFIFO &amp; avalon mm user guides.https://www.intel.com/content/www/us/en/programmable/support/literature/lit-ip.htmlhttps://www.intel.cn/content/dam/altera-www/global/zh_CN/pdfs/literature/ug/ug_fifo.pdfhttps://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdfRegardsAnand

asuba · Answer

Hi AnandI already did the steps you mentioned above. But I am not sure how to acheive the control of making avalon to wait until the FIFO is not full . What   would be the procedure to do the same ?

anandraj_s_intel · Answer

​making avalon to wait until the FIFO is not full&gt;&gt;Avalone is in wait state until you given write or read signal from custom component.If fifo is full assert read signal &amp; deassert write and when if fifo is empty assert write signal &amp; deassert read.

asuba · Answer

Hi Yes I need to write in to DCFIFO when its not empty and need avalon to wait if the FIFO is full so that atleast once data is read out and its filled at same time.I am not sure how to get this avalon wait signals from qsys.

anandraj_s_intel · Answer

​Okay,You can write to fifo if empty/rdempty/wrempty asserted and full//rdfull/wrfull is deassert.Read from fifo if empty/rdempty/wrempty deassert and full//rdfull/wrfull is asserted.Which will make avalone bus wait.RegardsAnand

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Using DCFIFO from Quartus IP in Qsys with avalon mm at write side

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