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ASuba's avatar
ASuba
Icon for New Contributor rankNew Contributor
7 years ago

Using DCFIFO from Quartus IP in Qsys with avalon mm at write side

Hi all Hi Iam workign with Cyclone v FPGA. I am using DCFIFO from Quartus IP mapped to avalon mm interface where write side of FIFO is connected to avalon mm and read side is to the custom IP in Q...
AnandRaj_S_Intel's avatar
AnandRaj_S_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

A slave asserts wait request when unable to respond to a read or write request. Forces the master to wait until the interconnect is ready to proceed with the transfer.

You have should have wait logic in slave design to control it.

Please open a new case for further Query.

Regards

Anand