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ASuba
New Contributor
New ContributorUsing DCFIFO from Quartus IP in Qsys with avalon mm at write side
Hi all Hi Iam workign with Cyclone v FPGA. I am using DCFIFO from Quartus IP mapped to avalon mm interface where write side of FIFO is connected to avalon mm and read side is to the custom IP in Q...
ASubaNew Contributor
New ContributorHi Anand
I already did the steps you mentioned above. But I am not sure how to acheive the control of making avalon to wait until the FIFO is not full . What would be the procedure to do the same ?
AnandRaj_S_Intel
Regular Contributor
Regular Contributormaking avalon to wait until the FIFO is not full
>>Avalone is in wait state until you given write or read signal from custom component.
If fifo is full assert read signal & deassert write and when if fifo is empty assert write signal & deassert read.
