New Contributor
Regular ContributorHi Athira,
Yes, you can do that using some logic in your custom component.
Refer below links design example and DCFIFO & avalon mm user guides.
https://www.intel.com/content/www/us/en/programmable/support/literature/lit-ip.html
https://www.intel.cn/content/dam/altera-www/global/zh_CN/pdfs/literature/ug/ug_fifo.pdf
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf
Regards
Anand
New ContributorHi Anand
I already did the steps you mentioned above. But I am not sure how to acheive the control of making avalon to wait until the FIFO is not full . What would be the procedure to do the same ?
Regular Contributormaking avalon to wait until the FIFO is not full
>>Avalone is in wait state until you given write or read signal from custom component.
If fifo is full assert read signal & deassert write and when if fifo is empty assert write signal & deassert read.
New ContributorHi
Yes I need to write in to DCFIFO when its not empty and need avalon to wait if the FIFO is full so that atleast once data is read out and its filled at same time.
I am not sure how to get this avalon wait signals from qsys.
Regular ContributorOkay,
Which will make avalone bus wait.
Regards
Anand
