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ASuba's avatar
ASuba
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7 years ago

Using DCFIFO from Quartus IP in Qsys with avalon mm at write side

Hi all Hi Iam workign with Cyclone v FPGA. I am using DCFIFO from Quartus IP mapped to avalon mm interface where write side of FIFO is connected to avalon mm and read side is to the custom IP in Q...
AnandRaj_S_Intel's avatar
AnandRaj_S_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi Athira,

Yes, you can do that using some logic in your custom component.

  1. Interface your DCFIFO and custom IP.
  2. Write a logic in custom IP to control DCFIFO read/write.

Refer below links design example and DCFIFO & avalon mm user guides.

https://www.intel.com/content/www/us/en/programmable/support/literature/lit-ip.html

https://www.intel.cn/content/dam/altera-www/global/zh_CN/pdfs/literature/ug/ug_fifo.pdf

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf

Regards

Anand

  • ASuba's avatar
    ASuba
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    7 years ago

    Hi Anand

    I already did the steps you mentioned above. But I am not sure how to acheive the control of making avalon to wait until the FIFO is not full . What would be the procedure to do the same ?

    • ASuba's avatar
      ASuba
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      7 years ago

      Hi Anand

      I am doing the same. I am sending data continuosly using the Software in Linux.(HPS system). How can I qualify the wait while I send the data continuosly ?

    • AnandRaj_S_Intel's avatar
      AnandRaj_S_Intel
      Icon for Regular Contributor rankRegular Contributor
      7 years ago

      ​Okay,

      1. You can write to fifo if empty/rdempty/wrempty asserted and full//rdfull/wrfull is deassert.
      2. Read from fifo if empty/rdempty/wrempty deassert and full//rdfull/wrfull is asserted.

      Which will make avalone bus wait.

      Regards

      Anand

    • ASuba's avatar
      ASuba
      Icon for New Contributor rankNew Contributor
      7 years ago

      Hi

      Yes I need to write in to DCFIFO when its not empty and need avalon to wait if the FIFO is full so that atleast once data is read out and its filled at same time.

      I am not sure how to get this avalon wait signals from qsys.