Using ALTLVDS_RX megacore

Question

Hi there,

I would be really grateful if someone could shed some light for me.... alright here's the scenario;

A LVDS stream(12 bit * 60 MHz = 720Mbps) is coming to my FPGA from an ADC, since it is in 12 bits and it is transmitted throught 2 wires (which means 1 channel? am i right), how can i ultilize the ALTLVDS_RX megacore provided by Altera (since the maximum deserialization factor selectable is just 10) to do deserialization ?? should i use 2 channel(in the parameterized core settings) and input HSMC_RX_D_P[0] to one of the pin while, HSMC_RX_D_N[0] to the other input?? or is there a trick of doing this? If i have to write my own shift register code, how should i address differential signalling in verilog? should i just consider " HSMC_RX_D_P[0]" and never have to consider "HSMC_RX_D_N[0]", since they are just 180 degree out of phase or the inverse of each other.

Michael :confused:

altera_forum · Answer

720Mbps stream with using LVDS pair results in 720MHz frequency. Are You suere Your FPGA can handle this?

There are no *_P or *_N wires.. You will have only one wire and it will rename (or actually add) automatically to _P and _N wires in the assignment editor or pin planner.

altera_forum · Answer

It is a DDR stream, so the source clock is only 360MHz.

altera_forum · Answer

Then check docu about ALTDDIO

altera_forum · Answer

--- Quote Start ---

Then check docu about ALTDDIO

--- Quote End ---

I'm not sure what you mean.

A DDR stream of X Hz clock rate has 2X bps. By consequence a DDR streem of Y bps has Y/2 Hz clock rate.

It would have been nice if you could point to the relevant document and page(s) showing this doesn't hold.

So the 360 MHz input clock should be feasible with the faster speed grades (c6 , C7) of Cyclone II onwards. For Stratix II all speed grades will probably do.

altera_forum · Answer

All differential signaling should have 2 wires (but i am not sure about what's channel meant by the core settings), one plus and one minus.

And yes, my LVDS is in DDR, so the frequency is only 360MHz.

Back to the original question, " how can i ultilize the ALTLVDS_RX megacore provided by Altera (since the maximum deserialization factor selectable is just 10) to do deserialization ?? should i use 2 channel(in the parameterized core settings) and input HSMC_RX_D_P[0] to one of the pin while, HSMC_RX_D_N[0] to the other input?? or is there a trick of doing this? If i have to write my own shift register code, how should i address differential signalling in verilog? should i just consider " HSMC_RX_D_P[0]" and never have to consider "HSMC_RX_D_N[0]", since they are just 180 degree out of phase or the inverse of each other. "

Forum Discussion

Using ALTLVDS_RX megacore

8 Replies

Recent Discussions

nSTATUS is sometimes asserted low during Agilex-F configuration when operating in PMBus slave mode

Agilex5 Engineering Silicon

MAX 10. No 3.0 V Schmitt Trigger I/O standard

Timing Behavior of Remote Update IP After Reset on Cyclone 10 GX (10CX150YF672E5G)

Agilex 5 A5EC065BB32AE5SR0 issue