Using ALTLVDS_RX megacore

All differential signaling should have 2 wires (but i am not sure about what's channel meant by the core settings), one plus and one minus.

And yes, my LVDS is in DDR, so the frequency is only 360MHz.

Back to the original question, " how can i ultilize the ALTLVDS_RX megacore provided by Altera (since the maximum deserialization factor selectable is just 10) to do deserialization ?? should i use 2 channel(in the parameterized core settings) and input HSMC_RX_D_P[0] to one of the pin while, HSMC_RX_D_N[0] to the other input?? or is there a trick of doing this? If i have to write my own shift register code, how should i address differential signalling in verilog? should i just consider " HSMC_RX_D_P[0]" and never have to consider "HSMC_RX_D_N[0]", since they are just 180 degree out of phase or the inverse of each other. "