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Altera_Forum
Honored Contributor
Honored ContributorUsing ALTLVDS_RX megacore
Hi there, I would be really grateful if someone could shed some light for me.... alright here's the scenario; A LVDS stream(12 bit * 60 MHz = 720Mbps) is coming to my FPGA from an ADC, ...
Altera_ForumHonored Contributor
Honored ContributorUsing ALTLVDS_RX: you could choose a factor of 6 and concatenate 2 6-bit readings to 12 bit. Maybe a bit tricky to align.
Doing it yourself isn't that difficult (as you are aware of). You don't need the fancy DPA to interface to high-speed ADCs (like T.I. and A.D. and others offer). In your logic module you just need to specify a single pin for each LVDS input/output-pair. The other (inverted) signal will be assigned by either the Assignment Editor or the Pin Planner, where you specify the applicable interface and voltage level. The positive pin will have the name you gave in the module definition, the other will get a'(n)' postfix to identify it as being the negative one of the pair.
