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Altera_Forum
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14 years ago

Using ALTLVDS_RX megacore

Hi there, I would be really grateful if someone could shed some light for me.... alright here's the scenario; A LVDS stream(12 bit * 60 MHz = 720Mbps) is coming to my FPGA from an ADC, ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I could type in the deserialization factor manually in Quartus 2 Version 9.0 or 9.1, but it does not allow me to manually type in a custom factor in Quartus 2 10.0sp1 that i am currently using.

Is there any way to go around this? can i generate the verilog code with 10 bit deserialization factor first, and then manually change the defram within the verilog settings into 12 bits?