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Altera_Forum
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15 years ago

Using ALTLVDS_RX megacore

Hi there, I would be really grateful if someone could shed some light for me.... alright here's the scenario; A LVDS stream(12 bit * 60 MHz = 720Mbps) is coming to my FPGA from an ADC, ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

720Mbps stream with using LVDS pair results in 720MHz frequency. Are You suere Your FPGA can handle this?

There are no *_P or *_N wires.. You will have only one wire and it will rename (or actually add) automatically to _P and _N wires in the assignment editor or pin planner.