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Altera_Forum
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15 years ago

Using ALTLVDS_RX megacore

Hi there, I would be really grateful if someone could shed some light for me.... alright here's the scenario; A LVDS stream(12 bit * 60 MHz = 720Mbps) is coming to my FPGA from an ADC, ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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Then check docu about ALTDDIO

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I'm not sure what you mean.

A DDR stream of X Hz clock rate has 2X bps. By consequence a DDR streem of Y bps has Y/2 Hz clock rate.

It would have been nice if you could point to the relevant document and page(s) showing this doesn't hold.

So the 360 MHz input clock should be feasible with the faster speed grades (c6 , C7) of Cyclone II onwards. For Stratix II all speed grades will probably do.