Forum Discussion
3 Replies
- Altera_Forum
Honored Contributor
Yes, that sounds reasonable.
Yes, the GPIO IP will allow you to generate a DDR signal you can drive to a pad. The same IP supports bidirectional ports as well. You can use 1.2V LVCMOS as the I/O standard, although that's not very common. As the tools will tell you a 1.2V I/O standard may have lower performance than I/O standards at higher voltages. Finally, as I frequently state on this forum - put a simple design together, constrain it and run it through Quartus. Quartus will answer all the questions you've asked. Cheers, Alex - Altera_Forum
Honored Contributor
Thanks Alex,
I am new to FPGA design and i dont have Altera in my PC: I am in a project design phase(so i came across a situation where i need an IO with 480Mbps LVCMOS 1.2V). Sorry for the inconvenience, I hope i can have a Altera Licence soon. Your reply is very useful for me. Regards Sujesh - Altera_Forum
Honored Contributor
Hie Sujesh,
just to addon. Like what Alex mentioned, it's not very common to use 1.2V LVCMOS I/O standard for DDR-related applications, =) However Quartus does not set restrictions based on the "common applications" of the I/O standards. Since you are new, i recommend you to checkout the Altera web which has a tonne of documentation on many topics that would be helpful to you. e.g.: https://www.altera.com/en_us/pdfs/literature/an/an348.pdf this should be a good guide for you on DDR-related applications, =) thanks, have a nice day!