Honored ContributorI am using the cyclone II series, and my global clock(32M,input_clk) is inputed by a dedicated clock input pin(clk0).
Now I need a clock which is 4MHz divided by input_clk, and output it to a dedicated clock output pin(PLL1_out)。 What can I do? I try to use a PLL, but it doesn't work, said:"Post divider max count exceeded". Any advice? Thank you!
Honored ContributorRight out of my head the slowest clock a cyclone II pll can generate is ~12MHz
plls in cyclone ii devices (http://www.altera.com/literature/hb/cyc2/cyc2_cii51007.pdf)Honored ContributorThe restriction is in the VCO frequency range and maximum divider count of 32. You have to use a post divider in logic. If a specific output timing is required for the output, you can supply the post divider with a phase shifted clock and adjust for the extra delay. The slightly increased jitter and timing inaccuracy shouldn't matter that much at 4 MHz.
Honored ContributorHonored ContributorIt's easy in this case, because Cyclone II has no real LVDS driver. You must use a resistor network at the output to achieve a correct LVDS level anyway. For a slow 4 MHz output, it's no problem to use a pseudo-differential output by connecting an inverter for the inverted pin. This is the only way to get a differential output at the dedicated clock output pins without driving it from the PLL.
Honored ContributorHonored ContributorHonored ContributorO, thank you, FvM.
I set the output pin to 2.5V independantly, and it worked.
