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Honored Contributor
Honored ContributorUse PLL between the dedicated clock input pin and output pin.
I am using the cyclone II series, and my global clock(32M,input_clk) is inputed by a dedicated clock input pin(clk0). Now I need a clock which is 4MHz divided by input_clk, and output it to a ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- so I have to set the output pin with LVDS standand --- Quote End --- Generally, not. You have to use the same I/O voltage and you have to keep some distance rules, but you can use different I/O standards in a bank.
