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It's easy in this case, because Cyclone II has no real LVDS driver. You must use a resistor network at the output to achieve a correct LVDS level anyway. For a slow 4 MHz output, it's no problem to use a pseudo-differential output by connecting an inverter for the inverted pin. This is the only way to get a differential output at the dedicated clock output pins without driving it from the PLL.
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To FvM:
Actually,I don't need a LVDS clock output, but my input clock already use the LVDS standand, and the output pin was assigned in the same I/O bank, so I have to set the output pin with LVDS standand.
In this situation, what can I do?
Honored Contributor
