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The restriction is in the VCO frequency range and maximum divider count of 32. You have to use a post divider in logic. If a specific output timing is required for the output, you can supply the post divider with a phase shifted clock and adjust for the extra delay. The slightly increased jitter and timing inaccuracy shouldn't matter that much at 4 MHz.
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I forgot to mention that I use the LVDS I/O standand on both the input clock and output clock. When I put a divider between the PLL and output pin, an error happened: Pin "clkout" with LVDS I/O standard must be driven by the external clock output of an enhanced PLL".
What's the solution? I totally have no idea.
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