Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Use PLL between the dedicated clock input pin and output pin.

I am using the cyclone II series, and my global clock(32M,input_clk) is inputed by a dedicated clock input pin(clk0). Now I need a clock which is 4MHz divided by input_clk, and output it to a ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

It's easy in this case, because Cyclone II has no real LVDS driver. You must use a resistor network at the output to achieve a correct LVDS level anyway. For a slow 4 MHz output, it's no problem to use a pseudo-differential output by connecting an inverter for the inverted pin. This is the only way to get a differential output at the dedicated clock output pins without driving it from the PLL.