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Honored Contributor
Honored ContributorUse PLL between the dedicated clock input pin and output pin.
I am using the cyclone II series, and my global clock(32M,input_clk) is inputed by a dedicated clock input pin(clk0). Now I need a clock which is 4MHz divided by input_clk, and output it to a ...
Altera_ForumHonored Contributor
Honored ContributorThe restriction is in the VCO frequency range and maximum divider count of 32. You have to use a post divider in logic. If a specific output timing is required for the output, you can supply the post divider with a phase shifted clock and adjust for the extra delay. The slightly increased jitter and timing inaccuracy shouldn't matter that much at 4 MHz.
